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PRELIMINARY DATA SHEET - Rev 1.0
Programmable Gain Amplifier
ARA2017
fEATuRES
* * * * * * * *
High Linearity, High Output Power Integrated Amplifier with Programmable Gain Control Attenuation Range: 0-58 dB, Adjustable in 2 dB Increments via a 3-wire Serial Control 33 dB Gain (at Minimum Attenuation) Low Distortion Products at Output Power Levels up to +64 dBmV Low Noise Figure and Output Noise Frequency range: 5-85 MHz 5 V Operation Materials set consistent with RoHS Directors. Surface Mount Package DOCSIS 3.0 Data Cable Modems and E-MTAs CATV Set Top Boxes S29 Package 28-Pin QfN 5 mm x 5 mm x 1 mm The ARA2017 supports output power levels of +64 dBmV while minimizing harmonic, distortion, and output noise levels. Its precision attenuator provides up to 58 dB of attenuation in 2 dB increments. The attenuator setting is programmed via a 3-wire serial interface, as is the output stage current, a feature which allows the device to be operated in reduced power modes for extended backup battery life in E-MTA applications. The ARA2017 is offered in a 28pin 5 mm x 5 mm x 1 mm QFN package.
APPLIcATIoNS
* *
PRoDucT DEScRIPTIoN
The ARA2017 is a highly linear, high output power, programmable gain amplifier optimized for DOCSIS 3.0 cable modem and E-MTA applications. Using a low noise input amplification stage and an ultra linear output driver amplifier, the device generates extremely low distortion products at the high output power levels required by DOCSIS 3.0 signals. Its balanced circuit design provides superior harmonic performance and an integrated digitally-controlled, multiple-stage precision step attenuator enables system solutions to meet DOCSIS power step accuracy requirements.
figure 1: functional Block Diagram
07/2008
ARA2017
figure 2: Pinout (X-Ray Top View) Table 1: Pin Description
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 NAME A1IN+ GND A1INGND A1OUTATTNINN/C GND CLOCK DATA ENBL N/C TX_EN VDD DEScRIPTIoN Amplifier A1 (+) Input Ground Amplifier A1 (-) Input Ground Amplifier A1 (-) Output and Supply Attentuator Input (-) No Connection Ground Clock Data Enable No Connection (Reserved for future use - leave floating) Transmit Enable Supply PIN 28 27 26 25 24 23 22 21 20 19 18 17 16 15 NAME A1OUT+ ATTNIN+ GND VATTN GND DEScRIPTIoN Amplifier A1 (+) Output and Supply Attentuator Input (+) Ground Attenuator Supply Ground
ATTNOUT+ Attentuator Output (+) A2IN+ A2OUT+ GND A2OUTGND A2INAmplifier A2 (+) Input Amplifier A2 (+) Output and Supply Ground Amplifier A2 (-) Output and Supply Ground Amplifier A2 (-) Input
ATTNOUT- Attentuator Output (-) N/C No Connection
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PRELIMINARY DATA SHEET - Rev 1.0 07/2008
ARA2017
ELEcTRIcAL cHARAcTERISTIcS
Table 2: Absolute Minimum and Maximum Ratings
PARAMETER Supply: VDD (pins 5, 14, 19, 21, 28), VATTN (pin 25)
RF Power at Inputs (pins 1, 3)
MIN 0 -0.5 -55
MAX +6 +40 VDD+0.5 +150
uNIT V dBmV V C
coMMENTS
differential into 200 V
Digital Interface (pins 9, 10, 11, 13) Storage Temperature
Stresses in excess of the absolute ratings may cause permanent damage. functional operation is not implied under these conditions. Exposure to absolute ratings for extended periods of time may adversely affect reliability.
Table 3: operating Ranges
PARAMETER Operating Frequency (f) Supply: VDD (pins 5, 14, 19, 21, 28) Digital Interface (pins 9, 10, 11, 13) Case Temperature (TC) MIN 5 +4.5 0 -20 TYP +5 +25 MAX 85 +5.5 VDD +85 uNIT MHz V V C
The device may be operated safely over these conditions; however, parametric performance is guaranteed only over the conditions defined in the electrical specifications.
Table 4: Digital Interface Specifications (VDD = +5.0 V)
PARAMETER Logic High Input Voltage: VIN,HIGH Logic Low Input Voltage: VIN,LOW MIN +2.0 0 TYP MAX VDD +0.8 uNIT V V
Note: 1. Logic control levels apply to the 3-wire programming bus (pins 9, 10, 11) and the transmit enable control (pin 13).
PRELIMINARY DATA SHEET - Rev 1.0 07/2008
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ARA2017 Table 5: Electrical Specifications VDD = +5.0 V, TX Enabled, (unless otherwise noted)
PARAMETER Gain Gain Flatness Gain Variation over Temperature Gain Range with Attenuator Incremental Attenuator Step Size 2nd Harmonic Distortion Level (2) 3rd Harmonic Distortion Level (2) 3rd Order Output Intercept (2) 1 dB Gain Compression (2) Noise Figure Output Noise Power Active / No Signal / Min. Atten. Set. Active / No Signal / Max. Atten. Set. Isolation (85 MHz) in Tx disable mode Differential Input Impedance Differential Output Impedance Output Impedance Output Return Loss (75 Ohm characteristic impedance) Output Voltage Transient Tx enable / Tx disable Total Supply Current (2) (pins 5, 14, 19, 21, 25, 28) Total Power Consumption MIN 34 58 1.5 +88 TYP 36 0.5 1.0 -0.02 2 -67 -72 +93 +73 2.5 MAX 37 2.5 -55 -55 uNIT dB dB dB/C dB dB dBc dBc dBmV dBmV dB Full gain @ 0 dB attenuator setting; Includes input balun loss Any 160 kHz bandwidth from 5 to 85 MHz +64 dBmV into 75 V +64 dBmV into 75 V 2 tone, +61 dBmV/tone coMMENTS 0 dB attenuation setting 5 to 42 MHz 5 to 85 MHz
-
-38.5 -53.8 60 200 75 75 -15 -12 50 7 340 10.5 1.7 52.5
400 -
dBmV dB V V V dB mVp-p mA W mW
between pins 1 and 3 (Tx enabled) between pins 19 and 21 with transformer Tx enabled Tx disabled 0 dB attenuator setting 24 dB attenuator setting Tx enabled (TX_EN high) Tx disabled (TX_EN low) Tx enabled (TX_EN high) Tx disabled (TX_EN low)
Notes: 1. As measured in ANADIGICS test fixture. (2) Measured using the maximum current setting-see Application Information section.
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PRELIMINARY DATA SHEET - Rev 1.0 07/2008
DATA PLoTS
figure ?: Gain vs frequency over Voltage
( Tc = 25 c ) figure 3: Gain vs frequency over Voltage (Tc = 25 8c)
+5V +5.25V +5.5V +4.75V +4.5V
o
ARA2017
36 35.5 35 34.5 34 33.5 33 0
VDD =
Gain (dB)
20
40
60
80
100
120
frequency (Mhz)
figure ?: Gain vs Temperature
( VDc 4: Gain vs 10MHz ) figure = +5V, f1 =Temperature (VDc = +5V, f1 = 10 MHz)
Gain dB NF dB
36 35 34
7 6 5 4 3 2 1 120
Gain(dB)
33 32 31 30 0 20 40 60 80
o
100
Temperature(case) c
PRELIMINARY DATA SHEET - Rev 1.0 07/2008
Nf(dB)
5
ARA2017
figure ?: Nf vs frequency over Voltage
figure 5: Nf vs frequency over Voltage
+5V +5.25V +5.5V +4.75V 4
VDD =
+4.5V
3.5
Nf(dB)
3
2.5
2 Tc = +25 c 0 20 40 60 80 100 120
o
1.5
frequency (Mhz)
figure ?: output Power at 1dB Gain compression (P1dB) vs. case Temperature
77 76.5 76
figure 6: output Power at 1dB Gain compres( VDD = +5V, f1 = 10MHz ) sion (P1dB) vs. case Temperature (VDD = +5V, f1 = 10MHz)
P1dB(dBmV)
75.5 75 74.5 74 73.5 73 0 20 40 60 80
o
100
120
case Temperature ( c)
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PRELIMINARY DATA SHEET - Rev 1.0 07/2008
ARA2017
figure ?: output Power at 1dB Gain compression (P1dB) vs Voltage figure 7: output Power at 1dB Gain compres77 76.5 76
o (sion=(P1dB) f1 = 10MHz ) Tc 25 c, vs Voltage (Tc = 25 8c, f1 = 10MHz)
P1dB (dBmV)
75.5 75 74.5 74 73.5 73 4.4
figure ?: output Third VoltageIntercept Point (oIP3) order (Vdc)
figure 8: output Third order Intercept Point (oIP3) vs. case Temperature
4.6
4.8
5
5.2
5.4
5.6
vs. case Temperature
95 94 93 92
oIP3(dBmV)
91 90 89 88 87 86 85 0 20 40 60 80
o
Vdd = +5Vdc f1 = 10mHz, f2 = 11mHz
100
120
case Temperature( c)
PRELIMINARY DATA SHEET - Rev 1.0 07/2008
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ARA2017
figure figure 9: output Third order Intercept Point ?: output Third order Intercept Point (oIP3) vs Voltage (oIP3) vs Voltage
92 91 90 89
oIP3 (dBmV)
88 87 86 85 84 83 82 4.4 4.6 4.8 5 5.2 5.4 5.6 Tcase = +25 c f1 = 10mHz, f2 = 11mHz
o
figure ?: Attenuator Accuracy over frequency
o figure 10: Attenuator Accuracy over frequency Tc = 25 c, Vdc = +5V (Tc = 25 8c, VDc = +5V)
Voltage (Vdc)
35
ATTENUATOR SETTING =
2dB
4dB
8dB
16dB
32dB
Measured Attenuation (dB)
30 25 20 15 10 5 0 10 20 30 40 50 60 70 80 90 100
frequency (MHz)
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PRELIMINARY DATA SHEET - Rev 1.0 07/2008
ARA2017
figure ?: Attenuator accuracy over Voltage
( Tc = +25 c, f1 = 10mHz ) figure 11:Attenuator Accuracy over Voltage (Tc = +25 8c, f1 = 10MHz)
35
ATTENUATOR SETTING =
o
2dB
4dB
8dB
16dB
32dB
Measured Attenuation(dB)
30 25 20 15 10 5 0 4.5 4.6 4.7 4.8 4.9 5 5.1 5.2 5.3 5.4 5.5
Supply Voltage, Vdd (Vdc)
35 30 25 20 15 10 5 0
figure 12: Attenuator Accuracy= 10mHz ) ( Vdc = +5V, f1 over Temperature (VDc = +5V, f1 = 10MHz) ATTENUATOR SETTING = 2dB 4dB 8dB 16dB 32dB
figure ?: Attenuator Accuracy over Temperature
Measured Attenuation(dB)
25
35
45
55
65
case Temperature ( c)
PRELIMINARY DATA SHEET - Rev 1.0 07/2008
o
75
85
95
9
ARA2017
(2)
figure 13: Test circuit
NOTES: 1. Pin 12 is reserved for future use. Do not connect (leave floating). (2) Input balun is used for evaluation test purposes only in 75 V system. Actual application does not require a 4:1 balun on the input.
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PRELIMINARY DATA SHEET - Rev 1.0 07/2008
ARA2017
LoGIc PRoGRAMMING
Programming Instructions The programming word is set through a 10 bit shift register via the data, clock and enable lines. The data is entered in order with the most significant bit (MSB) first and the least significant bit (LSB) last. The
enable line must be low for the duration of the data entry, then set high to latch the shift register. The rising edge of the clock pulse shifts each data value into the register.
Table 6: Programming Register
DATA BIT
fuNcTIoN
9
8
Current
7
6
5
4
Gain
3
2
1
0
0
1
Notes: 1. Refer to Application Information section for Current and Gain bit settings. 2. Data bit 0 should always be set to "1". 3. Data bit 1 is reserved for future use, and should be set to "0".
figure 14: Serial Data Input Timing
PRELIMINARY DATA SHEET - Rev 1.0 07/2008
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ARA2017
APPLIcATIoN INfoRMATIoN Transmit Enable / Disable output Transformer
The ARA2017 can be switched on (TX enable) and off (TX disable) via an asynchronous input TX_EN (pin 13). A logic high will turn the amplifier on. The gain and current settings are retained during Tx disable and do not need to be reloaded. The gain of the ARA2017 can be controlled via the 3-wire bus. Data bits D2 through D6 set the gain/ attenuator level, with 00000 being the min gain setting, and 11111 being the max gain setting. A new gain/ attenuator setting can be loaded while the PGA is on (TX enable), but will not take effect until TX_EN has been cycled off /on.
Matching the balanced output of the ARA2017 to a single-ended 75 V load is accomplished using a 1:1 turns ratio transformer. In addition to the balanced to single-ended conversion, this transformer provides the bias to the output amplifier stage via the center tap. The transformer also cancels even mode distortion products and common mode signals, such as the voltage transients that occur while enabling and disabling the amplifiers. As a result, care must be taken when selecting the transformer to be used at the output. It must be capable of handling the RF and DC power requirements without saturating the core, and it must have adequate isolation and good phase and amplitude balance. It also must operate over the desired frequency and temperature range for the intended application.
Gain/Attenuator Setting
output Stage current Setting
The ARA2017 consists of 2 gain stages. The input stage operates at a constant fixed current when TX is enabled. The current in the output stage can be controlled via the 3-wire bus. Data bits D7 - D9 set the current. 111 will set the output stage to maximum current for maximum linearity. The current can be lowered for improved efficiency at lower output power levels, or lower linearity requirements. 000 will turn both stages off, the same as TX disable. A new current setting can be loaded while the PGA is on (TX Enable), but will not take effect until TX_EN has been cycled off /on.
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PRELIMINARY DATA SHEET - Rev 1.0 07/2008
ARA2017
PAcKAGE ouTLINE
figure 15: S29 Package outline - 28 Pin 5 mm x 5 mm x 1 mm QfN
PRELIMINARY DATA SHEET - Rev 1.0 07/2008
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ARA2017
figure 16: Land Pattern
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PRELIMINARY DATA SHEET - Rev 1.0 07/2008
ARA2017
oRDERING INfoRMATIoN
oRDER NuMBER ARA2017RS29P8 TEMPERATuRE RANGE -20 oC to +85 oC PAcKAGE DEScRIPTIoN 28 Pin QFN Package 5 mm x 5 mm x 1 mm coMPoNENT PAcKAGING Tape and Reel, 2500 pieces per Reel
ANADIGIcS, Inc.
141 Mount Bethel Road Warren, New Jersey 07059, U.S.A. Tel: +1 (908) 668-5000 Fax: +1 (908) 668-5132 URL: http://www.anadigics.com E-mail: Mktg@anadigics.com IMPoRTANT NoTIcE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change prior to a product's formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the information they are using is current before placing orders.
ANADIGICS products are not intended for use in life support appliances, devices or systems. Use of an ANADIGICS product in any such application without written consent is prohibited.
wARNING
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PRELIMINARY DATA SHEET - Rev 1.0 07/2008

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